1. Field of the Invention
The present invention relates to an improved active matrix type display device and, in particular, an active matrix type display device which can provide a plurality of data input routes for writing a data signal into respective display elements and can make a normal display even if any break or imperfection occurs at a spot or spots in an associated interconnection.
2. Description of the Related Art
The development of active matrix type display devices has recently been made, in place of simple matrix type liquid crystal devices, which is excellent in their contrast and in their visibility-angle characteristic.
FIG. 1 shows a portion of a pixel array in a conventional active matrix type display device. This type of display device is disclosed, for example, in a document "IEEE Transactions ON ELECTRON DEVICES" Vol. ED-20, No. 11, November 1973, P 996. As shown in this document, a liquid crystal is employed for a display device with field effect transistors used as switching elements. C11 to C22 and T11 to T22 represent display elements and field effect transistors T11 to T22, respectively, and D1, D2 and G1, G2 represent data lines and scanning lines, respectively. That is, pixels as enclosed by broken lines in FIG. 1 are arranged in a matrix array with each constituted by the field effect transistor and display element. For a display to be made, one of scanning lines G1, G2 is selectively energized and a data signal is supplied to a corresponding data line to turn on the corresponding field effect transistor. The data signal is supplied via the turned-on field effect transistor to the corresponding display element. The display elements are displayed as light and dark according to whether or not the corresponding data-signal voltage is high or low.
If the number of scanning lines and data lines and hence that of switching elements are increased, it will be very difficult to manufacture them without any defects. In the conventional active matrix type display device as shown in FIG. 1, only one write-in route for writing the data signal into the display element is present and, if any defects occur, during manufacture, at the scanning lines, data lines or field effect transistors, no data signals are applied to the display elements so that no normal display can be carried out. The manufacturing yield will rapidly drop partly because the defects of component parts occur during manufacture and partly because the component parts have to be microminiaturized in spite of a great area involved. In order to solve the aforementioned problem, a plurality of FETs are connected in parallel to a single pixel electrode as shown, for example, in Japanese Patent Disclosure (Kokai) No. 56-77887 so that any defective FETs may be found at the stage of manufacture and removed from the rest of the FETs. It is, therefore, possible to employ good FETs alone. Another solution is disclosed in Japanese Patent Disclosure (KOKAI) No. 61-121034 in which two FETs are connected in parallel to a single pixel and their gates are connected to two scanning lines with a pixel sandwiched with these two lines and their source are connected commonly to a corresponding data signal line. In this case, if one of the two FETs is defective, the associated pixel can be driven with the other FET. Another solution is disclosed in Japanese Patent Disclosure (KOKAI) No. 61-128289. In a liquid crystal display device having a TFT array as shown in that KOKAI, a back-up electrode is provided adjacent to a main electrode and, if being broken at their connection, is connected to the main electrode, so that the downgrading of a display can be prevented without producing any panel image effects.
The conventional methods, however, require an additional step, such as the step of detecting defective elements or spots or the step of making a connection or a disconnection, thus offering an economical disadvantage.
The inventors disclose an active matrix type display device, in connection with Kokai No. 61-20091, which includes a plurality of data input routes for writing a data signal into a respective display elements. In the arrangement shown in FIG. 2, two FETs are provided for a respective display element so that each is connected to respective different display data line and scanning line. A plurality of routes for applying a display signal to the display element are provided and, even if defects occur at the data input route during manufacture, a normal display can be made without being affected by a periodic switching. It is thus possible to provide a better display than in the aforementioned prior art. In Japanese Patent Disclosure (KOKAI) No. 61-20091, an improved matrix array is disclosed where switching elements for adjacent two rows as provided for respective display elements are connected to a common scanning line so as to reduce the number of scanning lines and of scanning line drive circuits.
In this arrangement, display elements are arranged as an n rows.times.m columns matrix array in a manner defined by sequentially-numbered data lines and scanning lines. Since a top-down scanning is performed in an odd-numbered frame and bottom-up scanning is performed in an even-numbered frame, electric potentials on the electrodes of the display elements on the 1st, n/2-th and n-th rows in the array never vary uniformly with a variation in time. That is, in the display element electrodes on the n/2-th row, the write-in cycle becomes equal to the frame period and a variation of the voltage becomes regular. Since, in the display element electrodes on the 1st and n-th rows, long and short cycles are alternately repeated, an irregular potential appears on the electrodes of the display elements. For this reason, a difference in contrast ratio is produced at the central portion and at the upper and lower portions of a display panel, resulting in nonuniform image display. Furthermore, one of the data input routes is not available due to a break at its connection and the display quality is prominently downgraded at the upper and lower portions of the display panel due to an unbalance in the write-in cycle.